The commands are similar to those of normal SDRAM, except for the reassignment of the precharge and burst terminate opcodes:Ĭolumn address bit C0 is never transferred, and is assumed to be zero. Working at 1.2 V, LPDDR2 multiplexes the control and address lines onto a 10-bit double data rate CA bus. Timing parameters are specified for LPDDR-200 to LPDDR-1066 (clock frequencies of 100 to 533 MHz). Low-power states are similar to basic LPDDR, with some additional partial array refresh options. LPDDR2-N: Non-volatile ( NAND flash) memory.LPDDR2-S4: 4 n prefetch memory (like DDR2), or.LPDDR2-S2: 2 n prefetch memory (like DDR1),.It is not compatible with either DDR1 or DDR2 SDRAM, but can accommodate either: Samsung K4P4G154EC-FGC1 4 Gbit LPDDR2 chipĪ new JEDEC standard JESD209-2E defines a more dramatically revised low-power DDR interface. Samsung and Micron are two of the main providers of this technology, which is used in tablet and phone devices such as the iPhone 3GS, original iPad, Samsung Galaxy Tab 7.0 and Motorola Droid X. Additionally, chips are smaller, using less board space than their non-mobile equivalents. Additional savings come from temperature-compensated refresh (DRAM requires refresh less often at low temperatures), partial array self refresh, and a "deep power down" mode which sacrifices all memory contents. Most significantly, the supply voltage is reduced from 2.5 to 1.8 V. The original low-power DDR (sometimes retroactively called LPDDR1) is a slightly modified form of DDR SDRAM, with several changes to reduce overall power consumption. (DDR-4 and LPDDR-5 being the exceptions.) Memory modules implementing these higher frequencies are used in Apple MacBooks and gaming laptops.Īs with standard SDRAM, most generations double the internal fetch size and external transfer speed. They formalize overclocking the memory array up to 266.7 MHz for a 33% performance boost. The "E" versions mark enhanced versions of the specifications. In contrast with standard SDRAM, used in stationary devices and laptops and usually connected over a 64-bit wide memory bus, LPDDR also permits 16- or 32-bit wide channels. Bus width Properties of the different LP-DDR generations
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